1. Field of the Invention
The present invention pertains generally to electrical computers and data processing systems and more particularly to systems and methods for simulation and modeling.
2. Description of Related Art
A modern integrated circuit design and manufacturing process typically involves several stages. A Design stage is an initial phase in which a designer preferably captures a prototype circuit design using schematic design tools or preferably a Hardware Description Language (HDL). The prototype design is eventually recorded in a design representation such as a netlist or a design database. A designer may cycle in and out of the Design stage when guiding a design through multiple design iterations.
A Verification stage is a xe2x80x9ctestingxe2x80x9d phase in which a prototype design is logically tested to ensure that it matches its functional specification, that is, to verify the correctness of the design. Generally, verification involves logic simulation to verify that the circuit: (a) implements what it is supposed to do and (b) does not do what it is not supposed to do. This type of evaluation is typically performed during or immediately after the Design stage and often employs a variety of techniques, including functional verification with the use of an HDL, full logic simulation, and generation of functional test patterns, which represent input stimulus and simulated output results of the design. The designer provides input stimulus, which represents input signals for driving the input ports of the circuit design, to the logic simulation. The designer also typically generates a set of expected results for comparison to the simulated output results of the design. When errors are found, the designer preferably modifies the circuit design, the input stimulus, or the expected results and re-simulates the circuit until the logic simulation results are satisfactory.
During a Manufacturing stage, the design representation is used to generate photolithography masks used in semiconductor fabrication. The fabrication process yields semiconductor wafers in which numerous copies (i.e., chips) of the designed circuit are embedded. Preferably, each chip is rigorously tested in the Chip Testing stage to minimize the possibility of shipping a defective part to a customer.
In preparation for the subsequent Chip Testing stage, a designer typically develops input and output test patterns to be used when physically testing the manufactured chip on an Automated Test Equipment (ATE) system. To properly generate a set of test patterns that adequately tests the manufactured part, the designer performs fault simulations on the circuit design using an evolving set of input stimulus and simulated output results. Fault simulation is used to evaluate a set of test patterns intended to exhaustively exercise the variety of signal paths within the circuit. In this way, the designer can increase the probability of detecting manufacturing, design, or environmental defects (or xe2x80x9cfaultsxe2x80x9d) in the manufactured circuit. The goal of such exhaustive testing is to increase the probability that only defect-free production chips are packaged and sold to customers.
A fault in an integrated circuit chip can arise from a variety of origins. For example, defects in a fabricated transistor can cause a logic gate to sense a single value at an input port, regardless of the input value actually applied to that input port. This type of defect is termed a xe2x80x9cstuck-atxe2x80x9d fault, because the input value appears to be stuck at that single value. Other types of faults may include, without limitation, bridging faults, where two or more interconnections are shorted together, or CMOS stuck-open faults, where an electrical path through a p-channel or n-channel transistor of a CMOS logic acts like an open circuit. A designer uses fault simulation techniques to evaluate whether a particular set of test patterns can test substantially all logic paths in the chip for such faults and for other potential defects.
The results of fault simulation are generally an indication of which logic paths in the design were not tested adequately for faults. It is preferable to obtain a fault coverage of over 95% of the logic gates within a design with a set of test patterns. If fault simulation indicates a lower percentage of fault coverage, new test patterns may be added to the set or circuit changes may be implemented (e.g., providing an observable path to otherwise un-testable gates or adding special test circuitry, such as Build-In Self Test (BIST) or boundary scan architectures).
Fault simulation is a resource-intensive type of simulation, particularly when performed exclusively in software. Software-based fault simulation typically employs software-modeled design elements, such as behavioral models, representing portions of the circuit design. Modern fault simulation systems, however, also typically employ hardware acceleration, in which primitive logic gates are implemented in hardware and are used to model portions of the logic gates designed into the circuit. The hardware-modeled design gates operate on input test patterns much faster than a software-based counterpart, thereby greatly reducing the time required to perform the fault simulation.
Complex designs, however, often include logic blocks that are not easily modeled in a hardware accelerator. For example, some logic blocks in a design may not lend themselves to modeling using the primitives available in a hardware accelerator. Furthermore, some designs are so large and complex that the designer does not have enough primitive logic gates available in the hardware accelerator to model the entire design. In this situation, a designer may choose to model portions of the design in hardware and to model the remainder of the design in software using, for example, software-based behavioral models.
Fault simulation systems exist that coordinate the simulation of signal paths in the hardware-modeled portion and the software-modeled portion of the circuit. This coordination, however, typically slows down the simulation because of the increased communications and context switches between the two portions of the hybrid fault simulation (hardware and software). During fault simulation of a large design containing many software-modeled design elements, the communication between the host computer (simulating the software-modeled design element) and the hardware accelerator (simulating the hardware-modeled design element) has been identified as a primary cause of slow simulation speeds. Accordingly, need exists for a method that increases fault simulation speeds by minimizing the impact of such coordination.
A system and method in accordance with the present invention are useful to improve fault simulation speeds in circuit design representations that include software-modeled design elements and hardware-modeled designed elements. The present invention, for example, can use multiple fault simulation passes, which in combination can be performed faster than a single fault simulation pass in existing approaches.
It is therefore an advantage of an embodiment of the present invention that fault simulation speed can be improved when a design includes both hardware and software modeled design elements.
It is another advantage of an embodiment of the present invention that a design may be partitioned between hardware-modeled design elements and software-modeled design elements so as to enhance the fault simulation speed increase of a two-pass fault simulation method in accordance with the present invention. Additional objects, advantages, and novel features of the invention are set forth in the description which follows and will become more apparent to those skilled in the art when taken in conjunction with the accompanying drawings. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and accommodations particular pointed out in the appended claims.
To achieve the foregoing and other objects, in accordance with the purposes of the present invention, as embodied and broadly described herein, a system for performing fault simulation on an original design representation including a software-modeled design element and a hardware-modeled design element comprises an output signal pattern for output ports bounding the software-modeled design element; a test pattern for fault simulating the original design representation; a merge module that generates merged input stimulus by merging the output signal pattern with the test pattern; and a modified design representation based on the original design representation including a nonfunctional block replacing the software-modeled design element of the original design representation, the modified design representation being fault simulated using the merged input stimulus.
The present invention may also comprise, in accordance with its objects and purpose, a method comprising the operations of fault simulating in a hardware accelerator a first subset of a possible faults in a hardware-modeled design element of an original design representation; and fault simulating a second subset of the possible faults, including possible faults in a software-modeled design element in said original design representation, the second subset substantially including possible faults not included in the first subset.